The present invention relates to a method of manufacturing a semiconductor device, and specifically to a method of manufacturing an LSI device having a CMP process.
FIG. 3 is a partly cross-sectional view of a wafer short in ROS (Roll off starting point: length from a wafer plane end to a wafer end), which has a conventional CVD oxide film deposited thereon, and FIG. 4 is a diagram showing a wafer in-plane distribution of a polishing rate where CMP is effected on the wafer.
In FIG. 3, reference numeral 1 indicates a wafer, reference numeral 2 indicates a plane area of the wafer, reference numeral 3 indicates a wafer plane end, reference numeral 4 indicates a wafer end, and reference numeral 5 indicates a ROS thereof, respectively.
It is understood in the examples shown in FIGS. 3 and 4 that a distribution of a polishing rate has a characteristic in which the polishing rate is high at each wafer edge portion. In conclusion, the prior art shows that the polishing rate is not uniform within a wafer plane. It is desirable that in-plane uniformity of a polishing rate is satisfactory as the ideal. When a CMP process is actually effected on a device under circumstances where the uniformity is low, a problem arises in that the residual thickness of a polished film after having been polished, becomes ununiform.
Beside, FIG. 4 illustrates a wafer in-plane distribution of a polishing rate where polishing pads different in hardness are used. It is understood that the in-plane uniformity of the polishing rate is poor at a hard pad (indicated by a broken line in FIG. 4) as compared with a soft polishing pad (indicated by a solid line in FIG. 4) commonly used at present. It has become apparent that the hard pad is effective to improve flatness of the interior of a device chip. However, since the degradation of the wafer in-plane uniformity of the polishing rate becomes a problem, there is a need to improve the uniformity as common as the conventional soft pad.
As one cause that degrades the wafer in-plane uniformity of the polishing rate, deficiency in supply of a polishing slurry to the whole plane of the wafer has been estimated.
As shown in FIG. 3, a conventional sectional shape of a wafer end has a flat surface or plane up to about 0.7 mm (700 μm) as viewed from the wafer end with the object of ensuring a plane in the wafer surface to the utmost. The wafer has a hemispherical surface extending from the wafer plane end 3 to the wafer end 4.
Since the length (ROS) from the wafer plane end 3 to the wafer end 4 is small, the angle of contact between the wafer polishing pads becomes large, thus causing a phenomenon that the polishing slurry intended to flow toward the center of the wafer is dammed up. Therefore, a problem arises in that the deficiency in supply of the polishing slurry occurs.